An integrated circuit includes one or more regions or layers of conductive material that are isolated from other conductive regions or conductive layers. Such isolation may be in the form of junction isolation by juxtaposing regions or layers of opposite polarity next to one another. Isolation can also be achieved dielectrically by providing a dielectric region, layer or structure between selected conductive regions and between selected transistors or other devices in the integrated circuit. In certain devices, the entire integrated circuit is insulated from bulk substrate material by providing a buried dielectric layer. Such devices are termed silicon-on-insulator or SOI devices due to a buried insulative layer which isolates the active devices from the bulk silicon of the substrate. Certain SOI devices may also be formed using a bonded wafer technique. With that technique, a device wafer is bonded to a handle wafer by a silicon dioxide surface layer formed on either or both wafers. Thus, the bonded wafer has a buried dielectric layer beneath the device wafer.
While the above SOI techniques provide for vertical electrical dielectric isolation, other techniques laterally insulate adjacent transistors or devices. One such technique provides trenches around the devices. The trenches are patterned in the surface of the semiconductor substrate in which devices are formed or are to be formed. Trench isolation processes are commonly performed early in the process of fabricating an integrated circuit, prior to the major diffusions that form the transistors and other devices and before completion of thick thermal oxide growth. The trenches typically are filled with dielectric material and polysilicon. In U.S. Pat. No. 4,140,558, the trench in the substrate is filled with an oxide provided by thermal oxidation of the substrate material that forms the walls and floor of the trench. In U.S. Pat. No. 5,217,919, the trench in the substrate is filled with a thermal oxide during the step of local thermal oxidation. Such a so-called LOCOS step is generally performed after substantial diffusions form larger regions of the devices, e.g., after formation of the collector regions in bipolar devices or after the formation of well regions in MOS devices. LOCOS is a common step in the fabrication of many, but not all, devices. However, the fabrication of most devices includes a step of thermal oxidation where an oxide layer is grown and the thickness of the oxide layer exceeds 500 Angstroms.
Such prior art techniques have encountered or been the source of problems. Since the oxide that seals the sidewalls of the trench is thermally grown early in the prior art fabrication of the integrated circuit, the exposed top surface of the sidewall oxide is subject to etching that occurs later in the fabrication processes. In some cases an oxide etch may remove trench sidewall oxide, for example, in the complete oxide strip common before pad oxide growth in LOCOS processes. If the trench is filled with polysilicon or other material, the desired electrical insulation of the trench may be reduced and thereby adversely affect the overall reliability of the device. It has also been observed that crystal damage results from excess sidewall oxide growth. As pointed out above, the trench is formed and dielectrically isolated early in the fabrication of the integrated circuit. However, the oxide in the filled trench (particularly the oxide at the exposed top surface) will continue to grow when the wafer is subject to subsequent thermal oxide processes, e.g., the LOCOS step. During thermal oxidation, the substrate material, typically silicon, combines with oxygen to form silicon dioxide. So, each oxidized silicon atoms grows by the volume of two oxygen atoms. A molecule of silicon dioxide has approximately twice the volume of an atom of silicon. Such thermal oxidation effectively doubles the volume of the silicon. If the trench sidewall oxide growth is excessive, mechanical stresses are created by the trench oxide expansion and those stresses generate crystalline lattice defects in adjacent silicon device regions. Such defects increase device leakage and reduce overall yield. Such excess thermal oxide growth may also occur during any high temperature processing step such as diffusions and drive-in of implants.
Most integrated circuits have one or more buried layers. The buried layer may comprise a buried collector for a bipolar device or a buried drain for a field effect transistor. To make electrical contact between a surface region and a heavily doped buried layer within a semiconductor device, it is common practice to deep diffuse a dopant vertically from the surface through the device to the buried layer. Heating down diffuses a dopant from the surface and up diffuses a dopant from the buried layer. However the dopant also exhibits a lateral diffusion profile in addition to the vertical profile such that its down diffusion may fall short of meeting the buried layer up diffusion. In addition, lateral diffusion of the dopant may well cause undesirable interactions with other dopant diffusions. In either case, the lateral diffusion occupies a substantial volume. It is desirable to reduce that volume and thereby reduce the overall size of the device.
The aforementioned dopant diffusion difficulties may be overcome by introducing the contact dopant into the device through the sidewalls of an open trench prior to filling. Under these circumstances, the diffusion profile is predominantly lateral and less sensitive to the depth of the device islands, thereby ensuring reliable electrical contact between the device surface and the buried layer.
U.S. Pat. No. 4,717,682 discloses a semiconductor device characterized by junction isolation and a conductive layer of impurity-doped polysilicon on an inner surface of a trench. The trench is filled with an insulating material such as silicon dioxide. However, as discussed above, thick oxide deposits in trenches are susceptible to mechanical stresses and consequent crystalline lattice defects in adjacent regions of the device.
U.S. Pat. No. 4,910,572 discloses a device having junction isolation and a trench filled with a conductive material such as polysilicon that connects a buried layer with a surface contact. Conductive trenches leading to buried layers are also described in U.S. Pat. Nos. 5,298,779 and 4,980,747. Other examples of polysilicon filled trenches establishing contact to buried layers are included in U.S. Pat. Nos. 5,077,228; 4,520,552; and 3,847,687.
U.S. Pat. No. 4,468,856 describes a method for forming an ohmic contact to a semiconductor substrate that entails diffusing a dopant from a poly silicon layer downward to a buried layer. U.S. Pat. No. 5,183,781 discloses a semiconductor device with an etched contact hole lined with doped polysilicon and filled with undoped polysilicon, the hole being in contact with an underlying N-type diffusion layer as the source or drain region of an MOS transistor.